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m44c510 telefunken semiconductors rev. a2, 13jan98 1 (57) marc4 4-bit universal microcontroller the m44c510 is a member of the temic family of 4-bit single-chip microcontrollers. it contains rom, ram, up to 32 digital i/o pins, up to 10 maskable external interrupt sources, 4 maskable internal interrupts, a watchdog timer, 32-khz oscillator with programmable watch timer, 2 x 8-bit multifunction timer/counter module and a versatile on-chip system clock generation module. features 4 k x 8-bit application rom 256 x 4-bit ram 8 hardware and software interrupt priority levels bitwise maskable prioritized interrupts up to 10 external and 4 internal interrupts up to 32 i/o lines high drive ports (20 ma, v dd = 5 v) i/o ports bitwise configurable with combined inter- rupt handling (for serial i/o applications) 2 x 8-bit multifunction timer/counters 32-khz on chip oscillator with programmable prescaler/interval timer user definable on-chip system clock generation 4-mhz crystal, 4-mhz ceramic resonator or fully integrated rc oscillator ** benefits extremely low-power consumption minimal external components coded reset and watchdog timer ** power-on reset and abrown outo function power-down mode 2.4 v to 6.2 v supply voltage data retention down to 2 v in sleep mode efficient, hardware-controlled interrupt handling high-level programming language in qforth comprehensive library of useful routines pc based development tools (** mask option) marc4 system clock timer/ counter timer 0 timer 1 master reset te port 0 port 1 port 5 port b sclin sclout i/o bus rom ram 4-bit cpu core 5k x 8bit 256 x 4bit watch dog i/o i/o i/o test sleep nrst v dd v ss port 7 port a i/o port 4 i/o interrupt & reset prescaler av dd i/o i/o interrupt i/o interrupt port 6 real time clock oscin oscout melody & buzzer tim1 96 11515 i/o port c 4 44 4 442 4 2 figure 1. block diagram
m44c510 telefunken semiconductors rev. a2, 13-jan-98 2 (57) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 sclin bpc0 bp00 bp12 bp11 bp10 oscin oscout bp01 bp02 bp03 nrst hc_vss vdd bp43 bp42 bp41 bp40 bpb3 bpb2 bpb1 bpb0 bp70 bp71 bp72 bp73 bp53 bp52 bp51 bp50 tim1 bpa3 bpa2 bpa1 bpa0 te avdd bp61 bp60 sclout m44c510 13314 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 23 24 41 42 43 44 bpc1 bp13 vss n.c. figure 2. pin connections sso44-package table 1. pin description name function v dd power supply voltage +2.4 v to +6.2 v av dd analog power supply voltage +2.4 v to +6.2v v ss . hc_v ss circuit ground for high current i/o-lines and digital logic bp00 bp03 4 bidirectional i/o lines of port 0 automatic nibblewise configurable i/o bp10 bp13 4 bidirectional i/o lines of port 1(*) automatic nibblewise configurable i/o bp50 bp53 4 bidirectional i/o lines of high current port 5(*) bitwise configurable i/o bp70 bp73 4 bidirectional i/o lines of high current port 7(*) bitwise configurable i/o bpa0 bpa3 4 bidirectional i/o lines of port a(*) bitwise configurable i/o and as inputs to a port monitor module. optional coded reset inputs (*) bpb0 bpb3 4 bidirectional i/o lines of port b(*) bitwise configurable i/o and as inputs to a port monitor module bpc0 bpc1 2 bidirectional i/o lines of port c (*) bitwise configurable i/o bp60 bp61 2 bidirectional i/o lines of port 6 (*) bitwise configurable i/o or as external programmable interrupts bp40-t0out0 i/o line bp40 of port 4(*) configurable i/o or timer/counter 0 t0out0 bp41-t0out1 i/o line bp41 of port 4(*) configurable i/o or timer/counter 0 t0out1 bp42-buz high current i/o line bp42 of port 4(*) configurable i/o or buzzer output buz bp43-nbuz high current i/o line bp43 of port 4(*) configurable i/o or buzzer output nbuz tim1 dedicated bidirectional i/o for timer 1 sclin 4-mhz quartz crystal/ceramic resonator or trimming resistor input (mask-option dependent) sclout 4-mhz quartz crystal/ceramic resonator pin (mask-option dependent) oscin 32-khz quartz crystal pin (mask-option dependent) oscout 32-khz quartz crystal pin (mask-option dependent) te testmode input. this input is used to control the test modes (internal pull-down) nrst reset input (/output), a logic low on this pin resets the device. an internal watchdog or coded reset is indicated by a low pulse on this pin. (*) for mask options, please see the order information.
m44c510 telefunken semiconductors rev. a2, 13jan98 3 (57) table of contents 1 marc4 architecture 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 general description 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 components of marc4 core 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 rom 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 ram 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 registers 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 alu 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 instruction set 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6 i/o bus 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 interrupt structure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 hardware interrupts 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 software interrupts 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 hardware reset 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 clock generation 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 clock monitor mode 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 sleep mode 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 peripheral modules 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 addressing peripherals 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 bidirectional ports 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 port 0, port 1 bidirectional ports type 1 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 port 5, port 7, port c bidirectional ports type 2 18 . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 port a, port b bidirectional ports type 3 and port monitor function 18 . . . . . . . 2.2.4 port 6 bidirectional port type 4 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 port 4 bidirectional port type 5 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 tim1 bidirectional pin timer 1 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 interval timers / prescaler 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 interval timer registers 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 watchdog timer 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 timer/counter module (tcm) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 general timer/counter control registers 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 timer/counter in 16-bit mode 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 timer 0 modes 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 timer 1 modes 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 buzzer module 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 emulation 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 electrical characteristics 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 absolute maximum ratings 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 dc operating characteristics 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 ac characteristics 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pad layout 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 application examples 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ordering information 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
m44c510 telefunken semiconductors rev. a2, 13-jan-98 4 (57) 1 marc4 architecture ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ?? ?? ?? instruction decoder ccr tos alu ram pc rp sp x y program 256 x 4-bit marc4 core clock reset sleep memory bus i/o bus instruction bus reset system clock interrupt controller onchip peripheral modules 94 8973 memory figure 3. marc4 core 1.1 general description the marc4 microcontroller consists of an advanced stack based 4-bit cpu core and on-chip peripherals. the cpu is based on the harvard architecture with physi- cally separate program memory (rom) and data memory (ram). three independent buses, the instruction bus, the memory bus and the i/o bus are used for parallel commu- nication between rom, ram and peripherals. this enhances program execution speed by allowing both instruction prefetching, and a simultaneous communica- tion to the on-chip peripheral circuitry. the extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and effi- cient processing of hardware events. the marc4 is designed for the high-level programming language qforth. the core includes an expression and a return stack. this architecture allows high-level language pro- gramming without any loss in efficiency or code density. 1.2 components of marc4 core the core contains rom, ram, alu, a program counter, ram address registers, an instruction decoder and an interrupt controller. the following sections describe each functional block in more detail: 1.2.1 rom the program memory (rom) is mask programmed with the customer application program during the fabrication of the microcontroller. the rom is addressed by a 12-bit wide program counter, thus predefining a maximum pro- gram bank size of 4 kbytes. an additional 1 kbyte of rom exists which is used partly for a quality control self- test program. the remaining space is available for the application program. the access to this additional rom section is done by using a rom-bank switch.
m44c510 telefunken semiconductors rev. a2, 13jan98 5 (57) rom bank 0 (2k x 8 bit) basebank zero page (not available) bank 1 (1k x 8 bit) fffh 7ffh 1ffh 000h fffh bffh 7ffh common base bank address area 1f0h 1f8h 010h 018h 000h 008h 020h 1e8h 1e0h scall addresses 140h 180h 040h 0c0h 008h $autosleep $reset int0 int1 int2 int3 int4 int5 int6 int7 1e0h 1c0h 100h 080h zero page 000h 96 11517 figure 4. rom map of m44c510 the lowest user rom address segment is taken up by a 512-byte zero page which contains predefined start addresses for interrupt service routines and special sub- routines accessible with single-byte instructions (scall). the corresponding memory map is shown in figure 4. look-up tables of constants can also be held in rom and are accessed via the marc4's built-in table instruction. rom banking bank switching is fully supported by the compiler for customers programming with qforth. the marc4 switches from one rom bank to another by writing the new bank number to the rom bank register (rbr). conventional program space (power-up bank) resides in rom bank 0. each rom bank consists of a 4-kbyte ad- dress space whereby the lowest 2 kbyte is common to all banks, so that addresses between 000h and 7ffh always accesses the same rom data (see figure 4). when rom banking is used, the compiler will, if necessary, insert the program code to save and restore the condition of the rbr on bank switching. 1.2.2 ram the marc4 contains 256 x 4-bit wide static random access memory (ram). it is used for the expression stack, the return stack and data memory for variables and arrays. the ram is addressed by any of the four 8-bit wide ram address registers sp, rp, x and y. expression stack the 4-bit wide expression stack is addressed with the expression stack pointer (sp). all arithmetic, i/o and memory reference operations take their operands from, and return their result to the expression stack. the marc4 performs the operations with the top of stack items (tos and tos-1). the tos register contains the top element of the expression stack and works in the same way as an accumulator. this stack is also used for passing parameters between subroutines and as a scratch pad area for temporary storage of data. return stack the 12-bit wide return stack is addressed by the return stack pointer (rp). it is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. the return stack can also be used as a temporary storage area. the marc4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. the two stacks within the ram have a user- definable location and maximum depth. 1.2.3 registers the marc4 controller has seven programmable regis- ters and one condition code register. they are shown in figure 6. program counter (pc) the program counter (pc) is a 12-bit register that contains the address of the next instruction to be fetched from the rom. instructions currently being executed are decoded in the instruction decoder to determine the internal micro operations. for linear code (no calls or branches) the pro- gram counter is incremented with every instruction cycle. if a branch, call, return instruction or an interrupt is executed, the program counter is loaded with a new address. the program counter is also used with the table instruction to fetch 8-bit wide rom constants.
m44c510 telefunken semiconductors rev. a2, 13-jan-98 6 (57) ??? ??? ???? ???? ??????? ??????? ????? ????? ????? ????? ????? ????? ????? ??? ??? ram fch 00h autosleep ffh 03h 04h x y sp rp tos1 expression stack return stack global variables ram address register: 07h (256 x 4-bit) global variables 4-bit tos tos1 tos2 30 sp expression stack return stack ????? ????? 0 11 12-bit rp v 94 8975 figure 5. ram map rom banking register (rbr) the rom banking register is a 4-bit register whereby in the m44c510, only bit 2 is used. this indicates which rom bank is presently being addressed. the rbr is accessed with a standard qforth peripheral read or write instruction (in or out, port address `d' hex). ram address registers the ram is addressed with the four 8-bit wide ram address registers: sp, rp, x and y. these registers allow access to any of the 256 ram nibbles. expression stack pointer (sp) the stack pointer (sp) contains the address of the next-to- top 4-bit item (tos-1) of the expression stack. the pointer is automatically preincremented if a nibble is moved onto the stack, or postdecremented if a nibble is removed from the stack. every postdecrement operation moves the item (tos-1) to the tos register before the sp is decremented. after a reset the stack pointer has to be initialized with a >sp s0 o to allocate the start address of the expression stack area. return stack pointer (rp) the return stack pointer points to the top element of the 12-bit wide return stack. the pointer automatically pre- increments if an element is moved onto the stack or it postdecrements if an element is removed from the stack. the return stack pointer increments and decrements in steps of 4. this means that every time a 12-bit element is stacked, a 4-bit ram location is left unwritten. these locations are used by the qforth compiler to allocate 4-bit variables. after a reset, the return stack pointer has to be initialized with a>rp fch o. ram address register ( x and y ) the x and y registers are used to address any 4-bit item in the ram. a fetch operation moves the addressed nibble onto the tos. a store operation moves the tos to the addressed ram location. by using either the preincrement or postdecrement, addressing mode arrays in the ram can be compared, filled or moved. top of stack ( tos ) the top of stack register is the accumulator of the marc4. all arithmetic/logic, memory reference and i/o operations use this register. the tos register receives data from the alu, rom, ram or i/o bus. condition code register ( ccr ) the 4-bit wide condition code register contains the branch, the carry and the interrupt-enable flag. these bits indicate the current state of the cpu. the ccr flags are set or reset by alu operations. the instructions set_bcf, tog_bf, ccr! and di allow direct manipulation of the condition code register. carry/borrow ( c ) the carry/borrow flag indicates that borrow or carry out of arithmetic logic unit ( alu ) occurred during the last arithmetic operation. during shift and rotate operations, this bit is used as a fifth bit. boolean operations have no affect on the c flag. branch ( b ) the branch flag controls the conditional program branch- ing. should the branch flag have been set by a previous
m44c510 telefunken semiconductors rev. a2, 13jan98 7 (57) instruction, a conditional branch will cause a jump. this flag is affected by arithmetical, logical, shift, and rotate operations. interrupt enable ( i ) the interrupt-enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. after a reset, or on executing the di instruction, the interrupt-enable flag is reset, thus dis- abling all interrupts. the core will not accept any further interrupt requests until the interrupt-enable flag has been set again either by executing an ei, rti or sleep instruc- tion. tos ccr 0 3 0 3 0 7 0 7 0 7 0 11 rp sp x y pc b i program counter return stack pointer expression stack pointer ram address register (x) ram address register (y) top of stack register condition code register carry / borrow branch interrupt enable reserved 0 7 00 c 0 rom bank register rbr bank 96 11518 figure 6. programming model
m44c510 telefunken semiconductors rev. a2, 13-jan-98 8 (57) 1.2.4 alu ?? ?? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ????? ????? ????? ????? ????? ????? ????? ????? ????? ??????? ???? ???? tos1 ccr ram ???? ???? tos2 sp tos3 ????? ????? ????? ???????? ???????? ???????? tos alu tos4 94 8977 figure 7. alu zero-address operations the 4-bit alu performs all the arithmetical, logical, shift and rotate operations with the top two elements of the ex- pression stack (tos and tos-1) and returns the result to the tos. the alu operations affect the carry/borrow and branch flag in the condition code register (ccr). 1.2.5 instruction set the marc4 instruction set is optimized for the high- level programming language qforth. many marc4 instructions are qforth words. this enables the com- piler to generate a fast and compact program code. the cpu has an instruction pipeline which allows the control- ler to prefetch an instruction from rom at the same time as the present instruction is being executed. the marc4 is a zero-address machine. the instructions contain only the operation to be performed and no source or destination address fields. the operations are implicitly performed on the data placed on the stack. there are one and two byte instructions which are executed within 1 to 4 machine cycles. a marc4 machine cycle is made up of two system clock (syscl) cycles. most of the instruc- tions are only one byte long and are executed in a single machine cycle. 1.2.6 i/o bus the i/o ports and the registers of the peripheral modules (timer 0, timer 1, interval timer, watchdog etc.) are i/o mapped. all communication between the core and the on- chip peripherals takes place via the i/o bus and the associated i/o control. with the marc4 in and out instructions, the i/o bus enables a direct read or write access to one of the 16 primary i/o addresses. more about the i/o access to the on-chip peripherals is described in the aperipheral moduleso. the i/o bus is internal and is not accessible by the customer on the final micro- controller device, but is used as the interface for the marc4 emulation (see also the section aemulationo). 1.3 interrupt structure the marc4 can handle interrupts with eight different priority levels. they can be generated from the internal and external interrupt sources or by a software interrupt from the cpu itself. each interrupt level has a hard-wired priority and an associated vector for the service routine in the rom (see table 2, page 10). the programmer can postpone the processing of interrupts by resetting the in- terrupt enable flag (i) in the ccr. an interrupt occurrence will still be registered but the interrupt routine is only started after the i flag is set. all interrupts can be masked, and the priority individually software configured by pro- gramming the appropriate control register of the interrupting module (see section aperipheral moduleso).
m44c510 telefunken semiconductors rev. a2, 13jan98 9 (57) 7 6 5 4 3 2 1 0 priority level int5 active int7 active ??????? ??????? int2 pending swi0 int2 active ?????? ?????? int0 pending int0 active int2 rti rti int5 int3 active int3 rti rti rti int7 time main / autosleep main / autosleep 94 8978 figure 8. interrupt handling interrupt processing for processing the eight interrupt levels, the marc4 in- cludes an interrupt controller with two 8-bit wide ainterrupt pendingo and ainterrupt activeo registers. the interrupt controller samples all interrupt requests during every non-i/o instruction cycle and latches these in the interrupt pending register. whenever an interrupt request is detected, the cpu interrupts the program currently being execution, on condition that no higher priority interrupt is present in the interrupt active register. if the interrupt-enable bit is set, the processor enters an inter- rupt acknowledge cycle. during this cycle a short call (scall) instruction is executed to the service routine and the current pc is saved on the return stack. an inter- rupt service routine is finished with the rti instruction. this instruction sets the interrupt-enable flag, resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. when the interrupt-enable flag is reset (triggering of interrupt routines is disabled), the execution of new interrupt service routines is inhibited, but not the logging of the interrupt requests in the inter- rupt pending register. the execution of the interrupt is be delayed until the interrupt-enable flag is set again. note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). it should also be realized that automatic stacking of the rbr is not carried out by the hardware and so if rom banking is used, the rbr must be stacked on the expres- sion stack by the application program and restored before the rti. after a master reset (power-on, external or watchdog reset), the interrupt-enable flag and the inter- rupt pending and interrupt active registers are all reset. interrupt latency the interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being acti- vated. in the marc4, this is extremely short and takes between 3 to 5 machine cycles depending on the state of the core.
m44c510 telefunken semiconductors rev. a2, 13-jan-98 10 (57) table 2. interrupt priority table interrupt priority rom address maskable interrupt opcode int0 lowest 040h ye s c8h (scall 040h) int1 | 080h ye s d0h (scall 080h) int2 | 0c0h ye s d8h (scall 0c0h) int3 | 100h ye s e8h (scall 100h) int4 | 140h ye s e8h (scall 140h) int5 | 180h ye s f0h (scall 180h) int6 1c0h ye s f8h (scall 1c0h) int7 highest 1e0h ye s fch (scall 1e0h) 1.3.1 hardware interrupts table 3. hardware interrupts interrupt possible interrupt priorities rst interrupt mask function source 0 1 2 3 4 5 6 7 register bit nrst external x low level active watchdog # 1/2 2 sec. time out port a coded reset # level any inputs port a monitor * * * * paipr 3 any edge, any input port b monitor * * * * pbipr 3 any edge, any input port 60 external * * * * p6cr 1,0 any edge port 61 external * * * * p6cr 3,2 any edge interval timer inta * * itipr 0 1 of 8 frequencies (1 128 hz) interval timer intb * * itipr 1 1 of 8 frequencies (8 8192 hz) timer 0 * * * * t0cr 0 overflow/compare/ end measurement timer 1 * * * * t1cr 0 compare x = hardwired (neither optional or software configurable) # = customer mask option (see aordering informationo) * = software configurable (see aperipheral moduleso section for further details) in the m44c510, there are eleven hardware interrupt sources which can be programmed to occupy a variety of priority levels. each source can be individually masked by mask bits in the corresponding control registers. an overview of the possible hardware configurations is shown in table 3. 1.3.2 software interrupts the programmer can generate interrupts using the soft- ware interrupt instruction (swi) which is supported in qforth by predefined macros named swi0...swi7. the software triggered interrupt operates in exactly the same way as any hardware triggered interrupt. the swi instruction takes the top two elements from the expression stack and writes the corresponding bits via the i/o bus to the interrupt pending register. thus, by using the swi instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution.
m44c510 telefunken semiconductors rev. a2, 13jan98 11 (57) 1.4 hardware reset the master reset forces the cpu into a well-defined condition, is unmaskable and is activated independent of the current program state. it can be triggered by either initial supply power-up, a short collapse of the power sup- ply, a watchdog time out, activation of the nrst input or the occurrence of a coded reset on port a (see figure 9). a master reset activation will reset the interrupt enable flag, the interrupt pending register and the interrupt active register. during the reset phase, the i/o bus control sig- nals are set to 'reset mode' thereby initializing all on-chip peripherals. releasing the reset results in a short call instruction (op- code c1h) to the rom address 008h. this activates the initialization routine $reset which in turn initializes all necessary ram variables, stack pointers and peripheral configuration registers. power-on reset the fully integrated power-on reset circuit ensures that the core is held in a reset state until the minimum operat- ing supply voltage has been reached. a reset condition is also generated should the supply voltage drop momentarily below the minimum operating supply. external reset (nrst) an external reset can be triggered with the nrst pin. to activate an external reset, the pin should be low for a minimum of two machine cycles. coded reset (port a) the coded reset circuit is connected directly to the port a terminals. by using a mask option, the user can define a hardwired code combination (e.g., all pins low) which, if occurring on the port a, will generate a reset in the same way as the nrst pin. table 4. multiple key reset options no_rst not used (default) rst2 bpa0 & bpa1 rst3 bpa0 & bpa1 & bpa2 rst4 bpa0 & bpa1 & bpa2 & bpa3 note, that if this option is used, the reset is not maskable and will also trigger if the predefined code is written on to the port a by the cpu itself. care should also be taken not to generate an unwanted reset by inadvertently pass- ing through the reset code on input transitions. this applies especially if the pins have a high capacitive load. watchdog reset the watchdog's function can be enabled via a mask op- tion and triggers a reset with every watchdog counter overflow. to suppress the watchdog reset, the counter must be regularly reset by reading the watchdog register address (wdres). the cpu reacts in exactly the same manner as a reset stimulus from any of the above sources. port a port a i/o reset code cpu nrst v watch- power-on reset cpu reset rst pull-up code * time out v v wd reset * = mask option dog * dd ss dd 96 11556 figure 9. reset configuration
m44c510 telefunken semiconductors rev. a2, 13-jan-98 12 (57) 1.5 clock generation the m44c510 has a dual clock system, a system clock (syscl) for the core and a 32-khz subclock (subcl) for the time-keeping peripheral modules (see figure 10). each clock can be generated from independent on-chip oscillators or they can both be derived from the same high frequency syscl oscillator. this is mask selectable - al- lowing a choice of either an 4-mhz crystal, 4-mhz ceramic resonator or a rc oscillator. all the necessary os- cillator circuitry, with the exception of the actual crystal or resonator, are integrated on chip. therefore, if no exact timing is required, for example, it is possible to use the fully integrated rc oscillator, thus operating without any external components. an additional mask option enables a high resolution trim- mable rc oscillator whereby the syscl can be trimmed with an external resistor between sclin and v dd . in this configuration, the syscl frequency can be maintained stable to within a tolerance of 10% over the full operating temperature range. a syscl frequency of 2 mhz, for example, can be obtained by connecting a 200 k resistor (see figures 44, 48 and 49). some applications require only long-term time keeping or low resolution timing. in this case, an on-chip, low- power 32-khz crystal oscillator can be used to generate the subcl. this allows the core to go into sleep mode when not used, and therefore greatly reduces power con- sumption. if the full (2-mhz) timing resolution is required, then ei- ther the crystal or resonator oscillator should be used for syscl generation. should a suitable external 1...8-mhz or 32-khz clock source be available, then sclin (crystal oscillator con- figuration) or oscin respectively can be used as the input. note: a syscl frequency of 2 mhz leads an instruc- tion cycle time of 1 s. crystal oscillator ceramic resonator oscillator rc- oscillator oscin oscout r trim osc. select syscl toggle sclin sclout subcl 32khz crystal oscillator oscin oscout mask option divide by 64 out out * * * osc. select = to cpu to watchdog to prescaler to timer/counter to buzzer to timer/counter 96 11520 * * oscin oscout out * oscin oscout out * * figure 10. clock module
m44c510 telefunken semiconductors rev. a2, 13jan98 13 (57) 1.5.1 clock monitor mode 96 11521 syscl clocks nrst te bp10 oscillator test mode normal operation bp11 subcl clocks figure 11. clock monitoring for trimming purposes, the m44c510 can be put into a clock monitor mode. the test input (te) must therefore be pulsed high once, whereupon the syscl clock will appear on bp10 (port 1, bit 0) and subcl clock on port bp11 (port 1, bit 1). to put bp10 and bp11 back into normal operation, the reset must be reapplied (see fig- ure 11). 1.6 sleep mode the sleep mode is a shutdown condition which is used to reduce the average system power consumption in applica- tions where the m c is not fully utilized. in this mode, the system clock is stopped. the sleep mode is entered with the sleep instruction. this instruction sets the condition code register interrupt enable bit (i) to enable all inter- rupts and stops the core. during the sleep mode, the peripheral modules remain active and are able to generate interrupts. the m c exits the sleep mode with any interrupt or a reset. the sleep mode can only be maintained when no interrupt pending or active register bits are set. the application of the $autosleep routine ensures the correct function of the sleep mode. the total power con- sumption is directly proportional to the active time of the m c. for a rough estimation of the expected average sys- tem current consumption, the following formula should be used: i total (v dd ,f syscl ) = i sleep + (i dd * t active /t total ) i dd depends on v dd and f syscl . using a 32-khz crystal, the sleep current (i sleep ) is typically less than 1 m a. the active time of the core and the total emulation time are displayed in a separate window of the marc4 emulator software. 2 peripheral modules 2.1 addressing peripherals accessing the peripheral modules takes place via the i/o bus (see figure 12). the in or out instructions allow direct addressing of up to 16 i/o modules. a dual register addressing scheme has been adopted which addresses the aprimary registero directly. to address the aauxiliary reg- istero, the access must be switched with an aauxiliary switching moduleo. thus, a single in (or out) to the module address will read (or write) into the module pri- mary register. accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. byte-wide registers are accessed by multiple in (or out) instructions. extended addressing is used for more com- plex peripheral modules, with a larger number of registers. in this case, a bank of up to 16 subport registers are indirectly addressed with the subport address being initially written into the auxiliary register.
m44c510 telefunken semiconductors rev. a2, 13-jan-98 14 (57) aux. reg. subport 0 subport 1 subport fh subport eh i/o bus aux. reg. primary reg. bank of primary regs. primary reg. primary reg. (address pointer) auxiliary switch module i n d i r e c t s u b p o r t a c c e s s d u a l r e g i s t e r a c c e s s s i n g l e r e g i s t e r a c c e s s to other modules module m1 module asw module m2 module m3 address(m2) address(asw) out aux._data address(m2) out prim._data address(m2) out (primary register write) prim._data address(m3) out (primary register write) addr.(m1) addr.(asw) out addr.(sport) addr.(m1) out 1 2 (subport register write) sport_data addr.(m1) out 3 4 5 6 1 2 3 4 7 7 5 6 example of qforth program code addr.(mx) = module mx address aux._data = data to be written into auxiliary register prim._data = data to be written into primary register. addr.(m1) addr.(asw) out addr.(sport) addr.(m1) out 1 2 (subport register read) addr.(m1) in address(m2) address(asw) out address(m2) in (auxiliary register rea d) 5 6 address(m2) in (pr ima r y register rea d) 4 address(m1) address(asw) out address(m1) in (auxiliary register rea d) 1 2 address(m3) in (prima ry register read) 7 addr.(asw) = auxilia r y switch module addr ess addr.(m1) addr.(asw) out addr.(sport) addr.(m1) out 1 2 (subport register write byte) sport_data(lo) addr.(m1) out 3 addr.(m1) addr.(asw) out addr.(sport) addr.(m1) out 1 2 (subport register rea d byte) addr.(m1) in 3 sport_data(hi) addr.(m1) out 3 addr.(m1) in 3 sport_data(lo) = data to be written into subp ort (low nibble) sport_data(hi) = data to be written into subport (high nibble) addr.(sport) = subport address address(m2) address(asw) out aux._data(lo) address(m2) out (auxiliary register write byte) 5 6 aux._data(hi) address(m2) out 6 aux._data (lo)= data to be written into auxiliary register (low nibble) aux._data (hi) = data to be written into auxiliary register(high nibble) 3 ( auxiliary register write ) 96 11522 figure 12. example of i/o addressing
m44c510 telefunken semiconductors rev. a2, 13jan98 15 (57) table 5. m44c510 peripheral addresses port address name write /read register function module type see page 0 p0dat w/r port 0 data register/input data m3 17 1 p1dat w/r port 1 data register/input data m3 17 2 paipr w port a interrupt priority register m2 19 aux. paicr w port a interrupt control register 19 3 wdres r watchdog reset m3 25 pbipr w port b interrupt priority register m2 19 aux. pbicr w port b interrupt control register 19 4 p4dat w/r port 4 data register/pin data m2 22 aux. p4ddr w port 4 data direction register 18 5 p5dat w/r port 5 data register/pin data m2 18 aux. p5ddr w port 5 data direction register 16 6 p6dat w/r port 6 data register/pin data m2 20 aux p6cr w port 6 control register (byte) 21 7 p7dat w/r port 7 data register/pin data m2 18 aux. p7ddr w port 7 data direction register 16 8 asw w auxiliary switch register asw 13 9 tcm w/r data to/from subport addressed by tcx m1 25 aux. t0sr r timer 0 interrupt status register m1 31 tcsub w timer/counter subport address pointer m1 27 subport address 0 t0mo w timer 0 mode register m1 31 1 t0cr w timer 0 control register m1 32 2 t1mo w timer 1 mode register m1 40 3 t1cr w timer 1 control register m1 41 4 tcmo w timer/counter mode register m1 29 5 tcior w timer/counter i/o control register m1 28 6 tccr w timer/counter control register m1 27 7 tcip w timer/counter interrupt priority m1 28 8 t1cp w timer 1 compare register (byte) m1 41 t1ca r timer 1 capture register (byte) m1 41 9 t0cp w timer 0 compare register (byte) m1 33 t0ca r timer 0 capture register (byte) m1 33 a bzcr w buzzer control register m1 44 b-f reserved a padat w/r port a data register/pin data m2 18 aux. paddr w port a data direction register 16 b pbdat w/r port b data register/pin data m2 18 aux. pbddr w port b data direction register 16 c pcdat w/r port c data register/pin data m2 18 aux. pcddr w port c data direction register 16 d rbr w rom bank switch register m3 5, 7 e reserved f itfsr w interval timer frequency select register m2 23 aux. itipr w interval timer interrupt priority register 24
m44c510 telefunken semiconductors rev. a2, 13-jan-98 16 (57) 2.2 bidirectional ports with the exception of port 6 and port c, all other ports (0, 1, 4, 5, 7, a and b) are 4 bits wide. port 6 and port c have a data width of 2 bits (bit 0 and bit 1). all these ports may be used for data input or output. all ports are equipped with schmitt-trigger inputs and a variety of mask options for open drain, open source and full complementary out- puts and pull-up and pull-down transistors. all port data registers (pxdat) are i/o mapped to the primary address register of the respective port address, and the port data direction register (pxddr) to the corresponding auxiliary register. port data register (pxdat) primary register address: 'port address'hex bit 3* bit 2 bit 1 bit 0 pxdat pxdat3 pxdat2 pxdat1 pxdat0 reset value: 1111b * bit 3 msb, bit 0 lsb port data direction register (pxddr) auxiliary register address: 'port address'hex bit 3 bit 2 bit 1 bit 0 pxddr pxddr3 pxddr2 pxddr1 pxddr0 reset value: 1111b value: 1111b means all pins in input mode table 6. port data direction register (pxddr) code 3 2 1 0 function x x x 1 bpx0 in input mode x x x 0 bpx0 in output mode x x 1 x bpx1 in input mode x x 0 x bpx1 in output mode x 1 x x bpx2 in input mode x 0 x x bpx2 in output mode 1 x x x bpx3 in input mode 0 x x x bpx3 in output mode there are five different types of bidirectional ports: type 1 (ports 0 and 1) 4-bit wide, bidirectional ports with automatic full bus width direction switching. type 2 (ports 5 and 7) 4-bit wide, port c is a 2-bit wide, bitwise programmable high drive i/o port. type 3 (ports a and b) 4-bit wide, bitwise programmable bidirectional ports with optional key- board pull-ups. type 4 (port 6) 2-bit wide, bitwise programmable bidirectional ports with optional bus pullups and pro- grammable interrupt logic. type 5 (port 4) 4-bit wide, bitwise programmable bidirectional port also provides the i/o interface to timer 0 and the buzzer.
m44c510 telefunken semiconductors rev. a2, 13jan98 17 (57) 2.2.1 bidirectional port 0 and port 1 in this port type, the data direction register is not indepen- dently software programmable because the direction of the complete port is switched automatically when an i/o instruction occurs (see figure 13). the port can be switched to output mode with an out instruction and to input with an in instruction. the data written to a port will be stored into the output data latches and appears immedi- ately at the port pin following the out instruction. after reset, all output latches are set to '1' and the ports are switched to input mode. an in instruction reads the condition of the associated pins. note care must be taken when switching these bidirectional ports from output to input. the capacitive pin loading at this port, in conjunction with the high resistance pull-ups, may cause the cpu to read the contents of the output data register rather than the external input state. this can be avoided by using either of the following programming techniques: use two in instructions and drop the first data nibble. the first in switches the port from output to input and the drop removes the first invalid nibble. the second in reads the valid pin state. use an out instruction followed by an in instruction. with the out instruction, the capacitive load is charged or discharged depending on the optional pull-up /pull-down configuration. write a a1o for pins with pull-up resistors, and a a0o for pins with pull- down resistors. out in reset i/o bus d r s q q nq r master reset pxdaty *) mask options (data out) (direction) port 1 only bpxy v dd * pull-up * pull-down * * v dd * 14020 figure 13. bidirectional ports 0 and 1
m44c510 telefunken semiconductors rev. a2, 13-jan-98 18 (57) 2.2.2 port 5, port 7, port c bidirectional ports type 2 these, and all other bidirectional ports include a bitwise- programmable data direction register (pxddr) which allows the individual programming of each port bit as input or output. it also enables the reading of the pin condition in output mode. this is a useful feature for self testing and for serial bus applications. both type 2 and type 3 bidirectional ports have the same i/o logic. type 2, however, has an increased drive capa- bility and type 3, an additional low resistance pull-up as customer mask option. master reset q q bpxy mask options * * pxdaty pxddry i/o bus d i/o bus i/o bus * * pull-up pull-down v dd * static pull-up (ports a, b) (data out) (direction) * s d * s 96 11524 figure 14. bidirectional ports 5, 7, a, b and c 2.2.3 port a, port b bidirectional ports type 3 and port monitor function pxicr bpx3 bpx2 bpx1 bpx0 decoder connected to ports a and b (x = a or b) int5 int7 int3 int1 int5 int7 int3 int1 pxipr enx3 enx2 enx1 enx0 imax itrx prx1 prx2 00 01 10 11 prx1 prx2 96 11529 figure 15. port monitor module in addition to the standard i/o functions described in sec- tion 2.2.2, both port a (bpa3 bpa0) and port b (bpb3 bpb0) are equipped with port monitor modules. this module is connected across all four port pins (see fig- ure 19) and generates an interrupt should a pre-programmed transition occur on any of the selected pins. this allows interrupt driven port scanning without the power consuming task of continuously polling the port inputs. using the port interrupt control register (pxicr), pins can be individually selected. a non-selected pin cannot generate an interrupt. the port interrupt priority register (pxipr) allows masking of each interrupt, definition of the interrupt edge and programming of the interrupt priority levels. port a can also be used for a mask pro- grammable coded reset. for more information see section 1.4 hardware reset. the port interrupt priority registers paipr and pbipr are i/o mapped to the the primary address registers of the port monitor module addresses '2'h and '3'h respec- tively. the port interrupt control registers paicr and pbicr are mapped to the corresponding auxiliary registers.
m44c510 telefunken semiconductors rev. a2, 13jan98 19 (57) port monitor interrupt priority register (pxipr) x = 'a' (port a) or 'b' (port b) (port a) primary register address: '2'hex (port b) primary register address: '3'hex bit 3 bit 2 bit 1 bit 0 pxipr imx itrx prx2 prx1 reset value: 1111b imx interrupt mask itrx interrupt transition prx2..1 interrupt priority code table 7. port monitor interrupt priority register (pxipr) code 3 2 1 0 function x x 0 0 port monitor interrupt priority 7 x x 0 1 port monitor interrupt priority 5 x x 1 0 port monitor interrupt priority 3 x x 1 1 port monitor interrupt priority 1 x 0 x x port monitor interrupt on falling edge x 1 x x port monitor interrupt on rising edge 0 x x x port monitor interrupt enabled 1 x x x port monitor interrupt disabled port monitor interrupt control register (pxicr) x = 'a' (port a) or 'b' (port b) (port a) auxiliary register address: '2'hex (port b) auxiliary register address: '3'hex bit 3 bit 2 bit 1 bit 0 pxicr enx3 enx2 enx1 enx0 reset value: 1111b enx3 ... 0 port monitor input enable code table 8. port monitor interrupt control register (pxicr) code 3 2 1 0 function x x x 0 bit 0 can generate an interrupt x x x 1 bit 0 cannot generate an interrupt x x 0 x bit 1 can generate an interrupt x x 1 x bit 1 cannot generate an interrupt x 0 x x bit 2 can generate an interrupt x 1 x x bit 2 cannot generate an interrupt 0 x x x bit 3 can generate an interrupt 1 x x x bit 3 cannot generate an interrupt
m44c510 telefunken semiconductors rev. a2, 13-jan-98 20 (57) 2.2.4 bidirectional port 6 master reset q v dd v dd bp6y mask options * * p6daty i/o bus d in enable i/o bus * * pull-up pull-down v dd * static pull-up (data out) * * s 96 11525 y = 0 or 1 figure 16. bidirectional port 6 this 2-bit bidirectional port can be used as bitwise-pro- grammable i/o. the data is lsb aligned so that the two msb's will not appear on the port pins when written. the port pins can also be used as external interrupt inputs (see figures 15 and 16). both interrupts can be masked or inde- pendently configured to trigger on either edge. the interrupt priority levels are also configurable. the interrupt configuration and port direction is controlled by the port 6 control register (p6cr). an additional low resistance pull-up transistor (mask option) provides an internal bus pull-up for serial bus applications. in output mode (pxddr bit = 0), the respective port data register (pxdat) bit appears on the port pin, driven by an output port driver stage which can be mask pro- grammed as open drain, or full complementary cmos. with an in instruction the actual pin state can be read back into the controller at any time without changing the port directional mode. if the output port is mask config- ured as an open drain driver, the controller is able to receive the external data on this pin without switching into input mode as long as the output transistor is switched off. in input mode (pxddr bit = 1), the output driver stage is deactivated, so that an in instruction will directly read the pin state which can be driven from an external source. in this case, the state of the port data register (pxdat), although not appearing at the pin itself, remains unchanged. high resistance mask selectable pull-up or pull-down transistors are automatically switched onto the port pin in input mode. the port data register is written to the respective port address with an out instruction. the port 6 data register (p6dat) is i/o mapped to the primary address register of address '6'hex and the port 6 control register (p6cr) to the corresponding auxiliary register. the p6cr is a byte wide register and is written by writing the low nibble first and then the high nibble (see section 2.1 aaddressing peripheralso).
m44c510 telefunken semiconductors rev. a2, 13jan98 21 (57) port 6 data register (p6dat) primary register address: '6'hex bit 3 bit 2 bit 1 bit 0 p6dat not used not used p6dat1 p6dat0 reset value: xx11b the unused bits 2 and 3 are '0', if read. port 6 control register (p6cr) auxiliary register address: '6'hex bit 3 bit 2 bit 1 bit 0 p6cr first write cycle p61im2 p61im1 p60im2 p60im1 reset value: 1111b bit 7 bit 6 bit 5 bit 4 second write cycle p61pr2 p61pr1 p60pr2 p60pr1 reset value: 1111b p6xim2, p6xim1 port 6x interrupt mode/direction code p6xpr2, p6xpr1 bp6x interrupt priority code table 9. port 6 control register (p6cr) auxiliary address: '6'hex first write cycle second write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp60 in input mode interrupt disabled x x 1 1 bp60 set to priority 1 x x 0 1 bp60 in input mode rising edge interrupt x x 1 0 bp60 set to priority 3 x x 1 0 bp60 in input mode falling edge interrupt x x 0 1 bp60 set to priority 5 x x 0 0 bp60 in output mode interrupt disabled x x 0 0 bp60 set to priority 7 1 1 x x bp61 in input mode interrupt disabled 1 1 x x bp61 set to priority 0 0 1 x x bp61 in input mode rising edge interrupt 1 0 x x bp61 set to priority 2 1 0 x x bp61 in input mode falling edge interrupt 0 1 x x bp61 set to priority 4 0 0 x x bp61 in output mode interrupt disabled 0 0 x x bp61 set to priority 6
m44c510 telefunken semiconductors rev. a2, 13-jan-98 22 (57) bidir. port in_enable data in p6cr: bp60 bidir. port in_enable data in bp61 cr0 decode decode decode decode int6 int4 int2 int0 int7 int5 int3 int1 i/o bus cr7 cr6 0 1 0 0 0 1 11 int6 int4 int2 int0 cr5 cr4 0 1 0 0 0 1 11 int7 int5 int3 int1 cr3 cr2 0 1 0 0 0 1 11 dir. int edge int disabled dir. dir. edge edge mask mask cr1 cr0 out yes yes in in in no no cr7 cr6 cr5 cr4 cr3 cr2 cr1 96 11526 figure 17. port 6 external interrupts 2.2.5 bidirectional port 4 the bidirectional port 4 is both a bitwise configurable i/o port and provides the external pins for both the timer 0 and the internal buzzer generator. as a normal port, it per- forms in exactly the same way as bidirectional port type 2 (see figure 14). two additional multiplexers allow data and port direction control to be passed over to other inter- nal modules (timer 0 or buzzer). each of the four port 4 pins can be individually switched by the timer/counter i/o register (tcio). figure 17 shows the internal inter- faces to port 4. master reset q v dd v dd bp4y mask options * * p4daty i/o bus d i/o bus i/o bus * * pull-up pull-down (data out) * * s 96 11527 p4ddry s q d tcioy t0out (direction) tdir t0in figure 18. bidirectional port 4
m44c510 telefunken semiconductors rev. a2, 13jan98 23 (57) 2.2.6 tim1 dedicated timer 1 i/o t1in (timer 1 input) t1out (timer 1 output) t1dir (direction control) v dd v dd tim1 mask options * * * * pull-up pull-down * * 96 11528 figure 19. bidirectional pin tim1 tim1 is a dedicated bidirectional i/o stage for signal communication to and from the timer 1 in the timer/ counter module (see figure 18). it has no i/o bus interface and is not directly accessible from the cpu. the direction control is performed from the timer/counter configura- tion registers. 2.3 interval timers / prescaler the interval timers are based on a frequency divider for generating two independent time base interrupts. it is driven by subcl generated by the clock module (see fig- ure 10) and consists of a 15-stage binary divider and two programmable multiplexers for selecting the appropriate interrupt frequencies for each interrupt source (see fig- ure 20). each multiplexer is completely independent and is controlled by the common interval timer frequency select register (itfsr). buffer registers store the respec- tive frequency select codes and ensure complete programming independence of each interrupt channel. interrupt masking and programming of the interrupt priority levels is performed with the aid of the interval timer interrupt priority register (itipr). subcl ck 8092hz 4096hz 2048hz 1024hz 256hz 128hz 64hz 32hz 8hz 4hz 2hz 1hz 1hz 0h 1h 2h 3h 4h 5h 6h 7h 2hz 4hz 8hz 16hz 16hz 32hz 64hz 128hz 8hz 8h 9h ah bh ch dh eh fh 16hz 64hz 256hz 1024hz 2048hz 4096hz 8192hz itfsr fs1 fs2 fs3 fs0 buffer buffer itipr mia pra prb mib inta 8:1 mux intb 8:1 mux int5 int1 int6 int2 r 15-stage binary counter 2 2 222 2 22 2 22 2 222 3 45678 9 10 11 12 13 14 15 (e.g. subcl = 32 khz) 96 11530 figure 20. interval timers / prescaler
m44c510 telefunken semiconductors rev. a2, 13-jan-98 24 (57) 2.3.1 interval timer registers the interval timer frequency select register (itfsr) is i/o mapped to the primary address register of the pre- scaler/ interval timer address ('f'hex) and the interval timer interrupt priority register (itipr) to the corre- sponding auxiliary register. the interrupt masks mia and mib enable interrupt masking of inta and intb respec- tively. each interrupt source can be programmed with pra and prb to one of two interrupt priority levels. dis- abling both interrupts resets the interval timer. interval timer interrupt priority register (itipr) auxiliary register address (write only): 'f'hex bit 3 bit 2 bit 1 bit 0 itipr prb pra mib mia reset value: 1111b prb priority select interval timer interrupt intb pra priority select interval timer interrupt inta mib mask interval timer interrupt intb mia mask interval timer interrupt inta table 10. interval timer interrupt priority register (itipr) code 3 2 1 0 function x x 1 1 reset prescaler and halt x x x 1 interrupt a disabled x x x 0 interrupt a enabled x x 1 x interrupt b disabled x x 0 x interrupt b enabled x 1 x x interrupt a => priority 1 x 0 x x interrupt a => priority 5 1 x x x interrupt b => priority 2 0 x x x interrupt b => priority 6 interval timer frequency select register (itfsr) primary register address (write only): 'f'hex bit 3 bit 2 bit 1 bit 0 itfsr fs3 fs2 fs1 fs0 reset value: 1111b fs3 ... 0 frequency select code table 11.interval timer frequency select register (itfsr) code 3 2 1 0 function subcl divide by subcl = 32 khz code 3 2 1 0 function subcl divide by subcl = 32 khz 0 0 0 0 inta 2 15 select 1 hz 1 0 0 0 intb 2 12 select 8 hz 0 0 0 1 2 14 select 2 hz 1 0 0 1 2 11 select 16 hz 0 0 1 0 2 13 select 4 hz 1 0 1 0 2 9 select 64 hz 0 0 1 1 2 12 select 8 hz 1 0 1 1 2 7 select 256 hz 0 1 0 0 2 11 select 16 hz 1 1 0 0 2 5 select 1024 hz 0 1 0 1 2 10 select 32 hz 1 1 0 1 2 4 select 2048 hz 0 1 1 0 2 9 select 64 hz 1 1 1 0 2 3 select 4096 hz 0 1 1 1 2 8 select 128 hz 1 1 1 1 2 2 select 8192 hz the control bit fs3 determines whether the inta or the intb buffer register is loaded with the select code (fs2fs0). this allows independent programming of interval times for inta and intb.
m44c510 telefunken semiconductors rev. a2, 13jan98 25 (57) 2.4 watchdog timer 17-stage binary counter subcl ck rrrrrrrrrrrrrrrr r read wdres v * watchdog enable * * * * mask option 2 nrst master reset dd 14 2 15 2 16 96 11531 figure 21. watchdog timer the watchdog timer is a 17-stage binary divider clocked by subcl generated within the clock module (see fig- ures 10 and 21). it can only be enabled as a mask option whereby it must be periodically reset from the application program. the program cannot disable the watchdog. if the cpu find itself for an extended length of time in sleep mode or in a section of program that includes no watchdog reset, then the watchdog will overflow, thus forcing the nrst pin low. this initiates a master reset. the timeout period can be set to 0.5, 1 or 2 seconds (if subcl = 32 khz) by using a mask option. to reset the watchdog, the program must perform an in- instruction on the address wdres ('3'hex). no relevant data is received. the operation is therefore normally fol- lowed by a drop to flush the data from the stack. 2.5 timer/counter module (tcm) the tcm consists of two timer/counter blocks (timer 0 and timer 1) which can be used separately, or together as a single 16-bit counter/timer (see figure 22). each timer can be supplied by various internal or external clock sources. these can be selected and divided under program control using the timer/counter control register (tccr), the timer 0 control register (t0cr) and the timer 1 control register (t1cr). capture and compare registers (t0ca,t1ca,t0cp and t1cp) not only allow event counting, but also the generation of various timed output waveforms including programmable frequencies, modulated melody tones, pulse width modulated (pwm) and pulse density modulated (pdm) output signals. when in one of these signal generation modes, the capture register acts as timer shadow register, the current timer state is freezed whenever read by the cpu. the timer 0 is further equipped for performing a variety of time mea- surement operations. in this mode the capture register is used together with the gating logic for performing asynchronous, externally triggered snapshot measure- ments. these measurements include single input pulse width and period measurements and also dual input phase and positional measurement. the mode configuration is set in the timer 0 and timer 1 mode registers (t0mo and t1mo). each timer represents a single maskable interrupt source (t0int and t1int), the priority of which can be config- ured under program control. a timer 0 interrupt can be caused by any of three conditions (overflow, compare or end-of-measurement). the associated status register (t0sr) differentiates between these. a status register is not necessary in the timer 1 as an interrupt is caused only on a compare condition.
m44c510 telefunken semiconductors rev. a2, 13-jan-98 26 (57) 13909 ck prescaler rst gating control mux 4:1 mux 8:1 clock control up/down up/down counter t0ca compare t0cp reload control t0cr t0mo reset capture register compare register output control t0sr status register endof measu rement overflow int. enable int output control t1cp compare up/down counter t1ca compare register reload control carry t1mo clock control reset capture register mux 2:1 mux 8:1 t1cr rst prescaler ck mux 4:1 16bit mode int int. enable tccr tcmo t0out0 t1out t0in1 t0in0 syscl subcl subcl syscl t1in t0out1 t0out0 t0int t1int t1out timer 0 timer 1 < = cpu read/write registers overflow figure 22. timer/counter module
m44c510 telefunken semiconductors rev. a2, 13jan98 27 (57) 2.5.1 general timer/counter control registers with the exception of the timer 0 interrupt status regis- ter (t0sr), all the timer/counter registers are indirectly addressed using extended addressing as described in the section aaddressing peripheralso. an overview of all reg- ister and subport addresses is shown in table 4. the timer/counter auxiliary register (tcsub) holds the sub- port address of the particular register about to be accessed. care has to be taken to ensure that this subport access sequence is not interrupted. please refer to the 'hardc510.scr' hardware interface file as a programming guidline. timer/counter clock control register (tccr) subport address (indirect write access): '6'hex bit 3 bit 2 bit 1 bit 0 tccr t1cl2 t1cl1 t0cl2 t0cl1 reset value: 1111b t0cl2, t0cl1 timer 0 clock source select t1cl2, t1cl1 timer 1 clock source select table 12.timer/counter clock control register (tccr) code 3 2 1 0 function direction (tdir) bp40* tim1 x x 0 0 timer 0 clock = subcl out x x x 0 1 timer 0 clock = syscl out x x x 1 0 timer 0 clock = timer1 output (t1out connected internally) out x x x 1 1 timer 0 clock = t0in0 ( bp40*) in x 0 0 x x timer 1 clock = subcl x out 0 1 x x timer 1 clock = syscl x out 1 0 x x timer 1 clock = timer 0 output (t0out0 connected internally) x out 1 1 x x timer 1 clock = tim1 x in * if tcio0 = low (connects timer 0 to port 4) the timer/counter clock control register (tccr) controls the clock source to both timer 0 and timer 1 prescalers. if an external clock source (on bp40 or tim1) is selected, then the corresponding port direction is automatically switched to input mode (see figure 23). note: the tcio0 bit must be set low for the bp40 external timer/counter access.
m44c510 telefunken semiconductors rev. a2, 13-jan-98 28 (57) timer/counter interrupt priority register (tcip) the timer/counter interrupt priority register (tcip) is used to configure the timer 0 and timer 1 interrupt priority levels. subport address (indirect write access): '7'hex bit 3 bit 2 bit 1 bit 0 tcip t1ip2 t1ip11 t0ip2 t0ip1 reset value: 1111b t0ip2, t0ip1 timer 0 interrupt priority code t1ip2, t1ip1 timer 1 interrupt priority code table 13.timer/counter interrupt priority register (tcip) code 3 2 1 0 function x x 1 1 timer 0 interrupt priority 1 x x 1 0 timer 0 interrupt priority 3 x x 0 1 timer 0 interrupt priority 5 x x 0 0 timer 0 interrupt priority 7 1 1 x x timer 1 interrupt priority 0 1 0 x x timer 1 interrupt priority 2 0 1 x x timer 1 interrupt priority 4 0 0 x x timer 1 interrupt priority 6 timer/counter i/o control register (tcior) subport address (indirect write access): '5'hex bit 3 bit 2 bit 1 bit 0 tcior tcio3 tcio2 tcio1 tcio0 reset value: 1111b tcio3...0 timer / counter i/0 mode select table 14.timer/counter i/o control register (tcior) code 3 2 1 0 function x x x 1 bp40 standard port mode x x x 0 bp40 timer 0 clock input (t0in0) or timer 0 output (t0out0) x x 1 x bp41 standard port mode x x 0 x bp41 timer 0 gate input (t0in1) or timer 0 output (t0out1) x 1 x x bp42 standard port mode x 0 x x bp42 buzzer output (buz) 1 x x x bp43 standard port mode 0 x x x bp43 buzzer output (nbuz) by using the timer/counter i/o control register (tcior) the program can configure the respective port 4 pins as either standard data i/o ports or as external signal ports for the timer 0 and buzzer. the timer 1 uses a dedi- cated i/o pin tim1, whose direction is controlled solely by the tccr (see figure 23). it should be noted that if a tcior bit is set low, then the corresponding port data direction register (p4ddr) bit no longer influences the port direction. in the case of bp40 and bp41, the port direction is then controlled entirely by the timer/counter configuration registers (tccr,t0mo), while pins bp42 and bp43 become unidirectional buzzer outputs.
m44c510 telefunken semiconductors rev. a2, 13jan98 29 (57) bp40 buzzer buz nbuz timer 0 t0in0 t0in1 t0out0 t0out1 timer 1 t1in t1out p4dat0 p4ddr0 bp41 p4dat1 p4ddr1 bp42 p4dat2 p4ddr2 bp43 tim1 tccr tccr tcio0 pwm,pdm melody,counter t0mo to cpu select ext. clock select ext. clock 96 11533 to cpu tcio1 to cpu tcio2 '0' p4dat3 p4ddr3 to cpu tcio3 '0' figure 23. timer/counter and buzzer external interface timer/counter mode register (tcmo) subport address (indirect write access): '4'hex bit 3 bit 2 bit 1 bit 0 tcmo t0ninv tc8 t1rst t0rst reset value: 1111b t0ninv timer 0 output (bp41) appears non-inverted at bp40 tc8 timer/counter in 8-/16-bit mode t1rst timer 1 reset/run t0rst timer 0 reset/run table 15.timer/counter mode register (tcmo) code 3 2 1 0 function x x x 0 timer 0 running x x x 1 timer 0 reset and halted x x 0 x timer 1 running x x 1 x timer 1 reset and halted x 0 x x timer/counter in 16-bit mode x 1 x x timer/counter in 8-bit mode 0 x x x inverted output bp41 appears on bp40 (bp40 = not bp41) 1 x x x non-inverted output bp41 appears on bp40 (bp40 = bp41)
m44c510 telefunken semiconductors rev. a2, 13-jan-98 30 (57) 2.5.2 timer/counter in 16-bit mode prescaler counter counter prescaler carry comparator compare register compare register comparator overflow/compare compare interrupt to tim1 8bit/16bit mux 96 11549 figure 24. 16-bit mode in 16-bit mode, timer 0 and timer 1 are cascaded thus forming a 16-bit counter (see figure 24) whereby, irre- spective of the state of timer 0 interrupt mask bit (t0im), the timer 1 counts both timer 0 overflow and compares interrupt events. these are generated according to the state of the timer 0 mode register as described in the t0mo table. the comparators are also cascaded so that when both timer 0 and timer 1 match their respective compare registers, the timer 1 generates both an output signal and a compare interrupt (if unmasked). in measurement modes, only timer 0 capture register is loaded with timer 0's contents on an end-of-measure- ment event. timer 1 capture register operates solely as a shadow register. there is no 16-bit capture operation, so the user program must check if timer 1 has incremented between reading the lower and higher byte. likewise, there is no automatic suppression of spurious interrupts which could conceivably be generated between writing timer 0 and timer 1 compare registers. 2.5.3 timer 0 modes the timer 0 mode configuration is defined in the timer 0 mode register (t0mo). the available modes and the effect on the timer 0 interrupt and interrupt flags is shown below. in all modes except the position measurement mode, timer 0 acts as an up-counter, the related clock fre- quency being defined by the selected clock source and the prescaler division factor. the counter can be reset and halted at any time by the t0rst bit of the tcmo register which also resets all the interrupt status flags and capture registers. whenever port 4 bp40 and bp41 pins are re- quired for timer 0 i/o, then the appropriate tcior enable bit must be set low. in this case, the port direction switching is handled automatically by the hardware. in modes where the bp40 is not used as a timer clock input or as a melody envelope output, the bp40 outputs the same signal as that appearing on bp41. with the help of the t0ninv bit of the timer/counter mode register (tcmo), the bp41 output can be inverted so that bp40 and bp41 form a differential output stage which can be used for directly driving piezo buzzers or small stepper motors.
m44c510 telefunken semiconductors rev. a2, 13jan98 31 (57) timer 0 mode register (t0mo) subport address (indirect write access): '0'hex bit 3 bit 2 bit 1 bit 0 t0mo t0mo3 t0mo2 t0mo1 t0mo0 reset value: 1111b t0mo3 ... 0 timer 0 mode code table 16.timer 0 mode register (t0mo) code 3 2 1 0 function assuming tcior1=tcior0=low interrupt set / t0sr affected bp40 (*3) bp41 cmp ofl eom 0 0 0 0 reserved 0 0 0 1 reserved 0 0 1 0 modulated melody mode envelope (out) tone (out) y/y y/y n/n 0 0 1 1 melody mode tone (out) tone (out) y/y y/y n/n 0 1 0 0 counter-auto reload (50% duty cycle) toggle (out) /clock (in) toggle (out) y/y y/y n/n 0 1 0 1 counter-free running (50% duty cycle) toggle (out) /clock (in) toggle (out) n/y y/y n/n 0 1 1 0 pulse density modulation pdm (out) /clock (in) pdm (out) n/y y/y n/n 0 1 1 1 pulse width modulation pwm (out) /clock (in) pwm (out) n/y y/y n/n 1 0 0 0 phase measurement signal 1 (in) signal 2 (in) n/n y/y y/y 1 0 0 1 position measurement signal 1 (in) signal 2 (in) (*1) (*2) n/n 1 0 1 0 low pulse width measurement clock (in) signal (in) n/y y/y y/y 1 0 1 1 high pulse width measurement clock (in) signal (in) n/y y/y y/y 1 1 0 0 counter- auto reload (strobe) strobe (out) /clock (in) strobe (out) y/y y/y n/y 1 1 0 1 counter-free running (strobe) strobe (out) /clock (in) strobe (out) n/y y/y n/y 1 1 1 0 period measurement (rising edge) clock (in) signal (in) n/y y/y y/y 1 1 1 1 period measurement (falling edge) clock (in) signal (in) n/y y/y y/y *1 note: the compare interrupt/status flag can only be set when counting up. *2 note: the overflow interrupt/status flag is set on both an overflow or an underflow. *3 note: the bp40 signals can be inverted if t0ninv=0 (tcmo register) timer 0 interrupt status register (t0sr) auxiliary register address (read access): '9'hex bit 3 bit 2 bit 1 bit 0 t0sr not used t0eom t0ofl t0cmp reset value: x000b note: the status register is reset automatically when read and also when timer 0 is reset. t0eom timer 0 end of measurement status flag t0ofl timer 0 overflow status flag t0cmp timer 0 compare status flag
m44c510 telefunken semiconductors rev. a2, 13-jan-98 32 (57) table 17.timer 0 interrupt status register (t0sr) code 3 2 1 0 function x x x 1 timer 0 compare has occurred (timer 0 = t0cp) x x 1 x timer 0 overflow or underflow has occurred x 1 x x timer 0 measurement completed the interrupt flags will be set whenever the associated condition occurs irrespective of whether the corresponding inter- rupt is triggered. therefore, the status flags are still set if the interrupt condition occurs when the interrupt is masked. to see exactly when the flags are set, see t0mo control code table 16, page 31. reading from the timer/counter auxiliary register will access the timer 0 interrupt status register (t0sr). timer 0 control register (t0cr) the t0cr is responsible for the predivision of the selected timer 0 input clock (see tccr). it can be divided or used directly as clock for the up/down counter. bit 0 is the mask bit for the timer 0 interrupt. subport address (indirect write access): '1'hex bit 3 bit 2 bit 1 bit 0 t0cr t0fs3 t0fs2 t0fs1 t0im reset value: 1111b t0fs3 ... 1 timer 0 prescaler division factor code t0im timer 0 interrupt mask table 18.timer 0 control register (t0cr) code 3 2 1 0 function x x x 1 timer 0 interrupt disabled x x x 0 timer 0 interrupt enabled 0 0 0 x timer 0 prescaler divide by 256 0 0 1 x timer 0 prescaler divide by 128 0 1 0 x timer 0 prescaler divide by 64 0 1 1 x timer 0 prescaler divide by 32 1 0 0 x timer 0 prescaler divide by 16 1 0 1 x timer 0 prescaler divide by 8 1 1 0 x timer 0 prescaler divide by 4 1 1 1 x timer 0 prescaler bypassed
m44c510 telefunken semiconductors rev. a2, 13jan98 33 (57) timer 0 compare register (t0cp) byte write subport address (indirect write access): '9'hex bit 3 bit 2 bit 1 bit 0 t0cp first write cycle t0cp3 t0cp2 t0cp1 t0cp0 reset value: xxxxb bit 7 bit 6 bit 5 bit 4 second write cycle t0cp7 t0cp6 t0cp5 t0cp4 reset value: xxxxb t0cp3 ... t0cp0 timer 0 compare register data (low nibble) first write cycle t0cp7 ... t0cp4 timer 0 compare register data (high nibble) second write cycle the compare register t0cp is 8-bit wide and must be accessed as byte wide subport (see section oaddressing peripher- als). first of all, the data is written low nibble and is then followed by the high nibble. any timer interrupts are automatically suppressed until the complete compare value has been transferred. timer 0 capture register (t0ca) byte read subport address (indirect read access): '9'hex bit 7 bit 6 bit 5 bit 4 t0ca first read cycle t0ca7 t0ca6 t0ca5 t0ca4 reset value: 0000b bit 3 bit 2 bit 1 bit 0 second read cycle t0ca3 t0ca2 t0ca1 t0ca0 reset value: 0000b t0ca7. .. t0ca4 timer 0 capture register data (high nibble) first read cycle t0ca3 ... t0ca0 timer 0 capture register data (low nibble) second read cycle note: if the timer is read (in pdm mode only) the bit order will appear reversed, so that t0ca0 =msb, t0ca1=msb-1 .... t0ca6=lsb+1, t0ca7 = lsb. the 8-bit capture register t0ca is read as byte wide subport. note, however, unlike the writing to the compare register, the high nibble is read first followed by the low nibble. the 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. during this transfer, the timer is free to continue counting. note: halting the timer after a capture/compare interrupt event will reset the capture register.
m44c510 telefunken semiconductors rev. a2, 13-jan-98 34 (57) timer 0 free running counter modes (strobe and 50% duty cycle) in the free running counter mode, timer 0 can be used as an event counter for summing external event pulses on bp40, or as a timer with an internal time-based clock. when enabled, the counter will count up generating an output signal on bp41 whenever the counter contents match the compare register (see figure 25). this signal can appear either as a strobe pulse or as a simple toggling of the output state (50% duty cycle) depending on the timer mode. interrupts (if not masked) are generated every 256 clocks on the overflow condition. the current counter state can be read at any time by reading the capture register,. the compare register has no effect on the counter cycle time and will not influence interrupts. timer clock t0out1 (bp41) overflow interrupt timer = compare register (= 4) timer resets on overflow 0 4 255 timer state strobe 50% duty cycle 1 2 35 6 4 1 2 35 6 0 255 255 4 1 2 35 6 0 ?? ?? ? 96 11534 figure 25. timer 0 free running counter mode timer 0 counter reload modes (strobe and 50% duty cycle) as in the free running mode, the counter can also be clocked from either an external signal on bp40 or from an internal clock source. in this mode, the counter repetition period is completely defined by the contents of the compare register (t0cp) (see figure 26). the counter counts up with the selected clock frequency. when it reaches the value held in the compare register, the counter then returns to the zero state. at the same time, depending on the selected timer mode, the bp41 either toggles or generates a strobe pulse. if the timer 0 interrupt is unmasked, a compare interrupt is also generated. the resultant output frequency f out = f in /2*(n+1) where n = compare value (n = 1 255). timer clock t0out1 (bp41) compare interrupt timer = compare register (= 7) resets timer 0 7 timer state 0 50% duty cycle strobe 4 1 2 35 6 7 0 4 1 2 35 6 7 0 4 1 2 35 6 ? ? ?? ?? ? ? 96 11535 figure 26. timer 0 counter reload mode
m44c510 telefunken semiconductors rev. a2, 13jan98 35 (57) motor chopping and mask options in the counter auto reload mode (50% duty cycle), mask options are available for generating a 1 khz or 2 khz frequency with duty cycles of 1/2, 3/8, 5/8 and 3/4. the resultant waveform is used as the chopping frequency for so called amotor choppingo. this technique allows the use of low cost, low voltage clock motors in applications where only higher sup- ply voltages are available. the resultant voltage waveforms are shown in figure 27. to obtain the required motor driver waveforms on bp40 and bp41 as shown in figure 28, the user program must modulate the timer 0 chopping frequency. this is performed by preloading port 4 data latches (p4dat0 and p4dat1) with '0' which sets the normal port 4 direc- tion register bits to output mode (p4ddr0 = p4ddr1 = '0') and switches the tcio0 and tcio1 register bits alternately to '0' on every chopping burst. the timer chopping signals are thus transferred to the port outputs. in the intermediate periods between bursts both tcio0 and tcio1 are set to '1' and the preloaded port 4 data latch outputs appear on the port outputs. timer clock t0out1 (bp41) timer 0 configuration reload mode, 50% duty cycle, comparator value = '3'hex (1 khz) or '7'hex (2 khz) timer clock = 32 khz (prescaler bypassed) * = mask option 3/8* 1/2 5/8* 3/4* 96 11536 figure 27. motor chopping waveforms bp41 bp40 chopping burst 96 11537 figure 28. motor driver output waveforms melody mode (with/without modulation) the non-modulated melody mode is identical to the auto- reload counter (50% duty cycle) mode. the melody tone frequency appearing on bp41 and/or bp40 is determined in exactly the same way as the value written into the comparator register. in the modulated melody mode, the m44c510 generates two output signals, a melody tone and an envelope pulse (see figure 29). the tone frequency output on bp41 is generated in exactly the same way as in the simple melody mode. while the envelope pulse on bp40 is a single pulse, of a clock period in duration which appears shortly after loading the compare value into the compare register. in this mode, an analog switch is activated between the bp40 and bp41 outputs (see figure 30). with the external capacitor connected, the resultant signal on bp41 exhibits a melody chime effect with an exponential decay.
m44c510 telefunken semiconductors rev. a2, 13-jan-98 36 (57) timer clock t0out0 (bp40) compare interrupt timer = compare register resets timer 0 7 ti mer state 0 t0out1 (bp41) new value (=7) loaded into compare register 4 1 2 35 6 0 7 4 1 2 35 6 0 7 4 1 2 35 6 0 7 4 1 2 35 6 7 4 1 2 35 6 96 11538 figure 29. modulated melody mode t0out0 t0out1 v analog switch modulated melody mode bp41 bp40 t0out0 (melody output) t0out1 (envelope) bp40 bp41 v 10...47uf r (optional) piezo buzzer v dd ss dd v ss 96 11539 figure 30. modulated melody output circuit
m44c510 telefunken semiconductors rev. a2, 13jan98 37 (57) timer 0 pulse width modulation mode a pulse width modulated (pwm) signal exhibits a fixed repetition frequency and a variable mark space ratio. it is often used as a simple method for d/a conversion, where the high period is proportional to the digital value to be converted. therefore by connecting a simple low-pass rc network to the pwm signal, the dc analog value can be gained. timer 0 generates the pwm signal by comparing the state of the free running up counter with the contents of the compare register (see figure 31). if the result is less than the compare register value, then the bp41 output is high. if the result is greater or equal to the compare register value, then the bp41 output is set low. thus, the high phase of the pwm signal is directly proportional to the compare register contents. a total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal to a continuous high signal. the pwm signal has a repetition period of 256 clock periods, an interrupt (if unmasked) being generated on every overflow event. care should be taken if the syscl clock is used as the pwm clock source because it may stop if the cpu goes into sleep mode (see mask options). ?? ?? ?? timer clock t0out1 (bp41) overflow interrupt timer = compare register (= 4) 04 255 timer state t_hi t_low t_hi = (comparator value)*clock period t_low = (255comparator value)*clock period 1 2 3 255 04 1 3 255 04 1 3 96 11540 figure 31. timer 0 pulse width modulation pulse density modulation mode pulse density modulation (pdm) is also used for simple d/a conversion. unlike the pwm signal,where the high and low signal phases are always continuous during a single repetition cycle, the pdm distributes these evenly as a series of pulses (see figure 32). this has the advantage that, if used together with an rc smoothing filter for d/a conversion, either the ripple is less than the pwm, or, for a corresponding ripple error, the filter components can be smaller or the clock frequency lower. to generate the pdm output on bp41, the pulse density is controlled by the contents of the compare register in the same way as the pwm generation. each of the pulses has a width equal to the counter clock period. pwm=0.25 pdm=0.25 pwm=0.75 pdm=0.75 repetition period 96 11541 figure 32. an example 4-bit pwm/pdm comparison
m44c510 telefunken semiconductors rev. a2, 13-jan-98 38 (57) period measurement modes (rising and falling edge) during the period measurement mode, the counter counts the number of either internal or external clocks in one period of the bp41 input signal (see figure 33). dependent on the mode chosen, this will be from rising edge to the next rising edge or conversely, falling edge to the following falling edge. on the trigger edge, the counter state is loaded into the capture register and subsequently reset. the measured value remains in the capture register until overwritten by the following measured value. interrupts can be generated by either an overflow condition or an end-of-measurement (eom) event. an 'eom' event signals the cpu that a new measured value is present in the capture register and can be read, if required. t0in1 (bp41) t_period oeomo interrupt c aptures an d resets t i mer falling edge triggered t_period rising edge triggered 96 11542 figure 33. period measurement pulse width measurement modes (high and low) in this mode, the selected clock source is gated to the counter for the duration of each input pulse received on bp41 (see figure 34). whether the measurement takes place during the high or low phase depends on the selected mode. at the end of each pulse, the counter state is loaded into the capture register and subsequently reset. interrupts can be gen- erated by either an overflow condition or an end-of-measurement (eom) event. an 'eom' event signals the cpu that a new measured value is present in the capture register can be read, if required. t0in1 (bp41) t_low t_high oeomo interrupt captures and resets timer 96 11543 figure 34. pulse width measurement
m44c510 telefunken semiconductors rev. a2, 13jan98 39 (57) phase measurement mode this mode allows the timer 0 to measure the phase misalignment between two 1:1 mark space ratio input signals con- nected to the bp40 and bp41 pins (see figure 35). the counter clock is gated with the phase misalignment period (tp), during which time the counter increments with the selected clock frequency. this misalignment period is defined as the period during which bp40 is high and bp41 is low. capturing and resetting of the counter always takes place on the rising edge of bp41. the measured value remains in the capture register until overwritten by the next measurement. interrupts can be generated by either an overflow condition or an end-of-measurement ('eom') event. an 'eom' event signals the cpu that a new measured value is present in the capture register and can be read, if required. t0in1 (bp41) t0in0 (bp40) oeomo interrupt tp tp tp captures & resets timer 96 11544 figure 35. phase measurement position measurement mode this mode is intended for the evaluation of positional sensors with biphase output signals. figure 36 illustrates a typical positional sensor system which delivers both incremental positional stepping signals and also directional information. the direction can be deduced from the relative phase of the two signals. therefore if bp40 is high on the rising edge of bp41, the moving mask travels to the left and if it is low then it travels to the right. the direction (left/right) informa - tion is used to set the direction of the up/down counter which enables the bp40 pulses to be counted. assuming that the system has been reset on a reference position, the counter will always hold the absolute current position of the mov- ing mask. this can be read by the cpu if necessary. this mode is the only one in which the counter is allowed to decrement. therefore, in this case it is possible for both an underflow or an overflow to occur. the overflow interrupt (if unmasked) will trigger on either of these conditions while the compare interrupt on the other hand will only trigger if the counter is counting upwards. to differentiate between an overflow or underflow, the compare value can be set to '0' hex, for example. an overflow would then set both the overflow and compare status flags while an underflow sets the overflow status flag only. t0in1 (bp41) t0in0 (bp40) typical sensor light light static mask moving mask t0in0 t0in1 left movement right movement timer n n+1 n+2 n+3 n n1 n2 n3 96 11545 figure 36. position measurement mode
m44c510 telefunken semiconductors rev. a2, 13-jan-98 40 (57) 2.5.4 timer 1 modes the timer 1 is aimed at performing event counting and timing functions (see figure 22). it has, unlike the timer 0, no gated clock or externally triggered capture modes. the counter counts up with an internal or external clock, depending on the state of the timer 1 control reg- ister (t1cr) and the timer/counter clock control register (tccr) and generates a compare interrupt whenever the counter matches the timer 1 compare regis- ter. this is the only timer 1 interrupt source. masking can be performed using the mask bit in the timer 1 control register (t1cr) and priority can be defined in the timer/ counter interrupt priority register (tcip). the tim1 pin is used by the timer 1 either as clock/event input or timer output. i/o control of the timer 1 pin tim1 is controlled entirely by the hardware, therefore if the tim1 is selected as an external clock or event source (in the tccr), there can be no timer 1 signal output. in this case, the timer would be used solely to generate interrupts. timer 1 mode register (t1mo) subport address (indirect write address): '2'hex bit 3 bit 2 bit 1 bit 0 t1mo t1mo3 t1mo2 t1mo1 t1mo0 reset value: 1111b t1mo3 ... 0 timer 1 mode control table 19.timer 1 mode register (t1mo) code 3 2 1 0 function compare interrupt 1 x 0 0 counter free running (50% duty cycle) yes 1 x 0 1 counter auto reload (50% duty cycle) yes 1 x 1 0 pulse width modulation yes 1 x 1 1 counter auto-reload (strobe output) yes x 0 x x increment on falling edge of clock x 1 x x increment on rising edge of clock 0 x x x reserved timer 1 control register (t1cr) the t1cr is responsible for the predivision of the selected timer 1 input clock (see tccr). it can be divided or used directly as clock for the up counter. bit 0 is the mask bit for the timer 1 interrupt. subport address (indirect write access): '3'hex bit 3 bit 2 bit 1 bit 0 t1cr t1fs3 t1fs2 t1fs1 t1im reset value: 1111b t1fs3 ... 1 timer 1 prescaler division factor code t1im timer 1 interrupt mask
m44c510 telefunken semiconductors rev. a2, 13jan98 41 (57) table 20.timer 1 control register (t1cr) code 3 2 1 0 function x x x 1 timer 1 interrupt disabled x x x 0 timer 1 interrupt enabled 0 0 0 x timer 1 prescaler divide by 256 0 0 1 x timer 1 prescaler divide by 128 0 1 0 x timer 1 prescaler divide by 64 0 1 1 x timer 1 prescaler divide by 32 1 0 0 x timer 1 prescaler divide by 16 1 0 1 x timer 1 prescaler divide by 8 1 1 0 x timer 1 prescaler divide by 4 1 1 1 x timer 1 prescaler bypassed timer 1 compare register (t1cp) byte write subport address (indirect write access): '8'hex bit 3 bit 2 bit 1 bit 0 t1cp first write cycle t1cp3 t1cp2 t1cp1 t1cp0 reset value: xxxxb bit 7 bit 6 bit 5 bit 4 second write cycle t1cp7 t1cp6 t1cp5 t1cp4 reset value: xxxxb t1cp3 ... t1cp0 timer 1 compare register data (low nibble) first write cycle t1cp7. .. t1cp4 timer 1 compare register data (high nibble) second write cycle the compare register t1cp is 8 bits wide and must be accessed as byte wide subport (see section aaddressing peripher- also). the data is written low nibble first, followed by high nibble. any timer interrupts are automatically suppressed until the complete compare value has been transferred. timer 1 capture register (t1ca) byte read subport address (indirect read access): '8'hex bit 7 bit 6 bit 5 bit 4 t1ca first read cycle t1ca7 t1ca6 t1ca5 t1ca4 reset value: 0000b bit 3 bit 2 bit 1 bit 0 second read cycle t1ca3 t1ca2 t1ca1 t1ca0 reset value: 0000b t1ca7 ... t1ca4 timer 1 capture register data (high nibble) first read cycle t1ca3 ... t1ca0 timer 1 capture register data (low nibble) second read cycle the 8-bit capture register t1ca is read as byte-wide subport. note, however, unlike the writing to the compare register, the high nibble is read first followed by low nibble. the 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. during this transfer, the timer is free to continue counting. note: halting the timer after a capture/compare interrupt event will reset the capture register.
m44c510 telefunken semiconductors rev. a2, 13-jan-98 42 (57) timer 1 counter free running (50% duty cycle) in the free running counter mode, the counter counts up with either an internal or external clock and cycles through all 256 timer states. on the clock following a match between the compare register (t1cr) and the counter, a compare interrupt (if unmasked) is generated and the tim1 pin is toggled (see figure 37). timer clock t1out (tim1) compare interrupt timer = compare register (= 4) 04 255 timer state 1 2 35 6 4 1 2 35 6 0 255 255 4 1 2 35 6 0 (clock set to rising edge) ? ?? ?? 50% duty cycle 96 11546 figure 37. timer 1 counter free running (50% duty cycle) timer 1 counter auto reload (strobe and 50% duty cycle) in the auto-reload mode, the counter counts up with either an internal or external clock. on the clock cycle following a match between the compare register (t1cr) and the counter, a compare interrupt (if unmasked) is generated. the tim1 output is either strobed or toggled and the counter reset (see figure 38). therefore, the counter cycle period is defined by the contents of the compare register. in 50% duty cycle mode the frequency of tim1 is: f tim1 = f in /2(n+1) where the compare value (n) =1 ... 255. timer clock t1out (tim1) compare interrupt timer = compare register (= 7) resets timer 0 7 ti mer state 0 50% duty cycle strobe 4 1 2 35 6 7 0 4 1 2 35 6 7 0 4 1 2 35 6 ? ?? ? (clock set to neg. edge) 96 11547 figure 38. timer 1 counter auto reload
m44c510 telefunken semiconductors rev. a2, 13jan98 43 (57) timer 1 pulse width modulation the timer 1 generates the pwm signal by comparing the state of the free running up counter with the contents of the compare register (see figure 39). if the result is less or equal to the compare register value, then the tim1 output is high. if the result is greater than the compare register value, then the tim1 output is set low. thus, the high phase of the pwm signal is directly proportional to the compare register contents. a total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal. the pwm signal has a repetition period of 256 clock periods, an interrupt (if unmasked) being generated on every compare event. care should be taken if the syscl clock is used as the pwm clock source because it will stop if the cpu goes into sleep. ? ?? ?? timer clock t1out (tim1) timer = compare register (=4) 04 255 timer state compare interrupt t_hi t_low t_hi = (comparator value) x clock period t_low = (256comparator value) x clock period 1 2 3 255 04 1 3 255 04 1 3 2 2 96 11548 figure 39. timer 1 pulse width modulation 2.6 buzzer module the buzzer is a 4 stage frequency divider which divides the subcl and depending on the state of the buzzer control register (bzcr) can output one of four frequencies. an external piezo or buzzer can be driven by the complementary buzzer outputs (buz and nbuz) which are directed to port 4 (bp42 and bp43) under control of the timer/counter i/o register (tcior) as shown in figure 23. when the buzzer is switched off, both of the buzzer outputs take up the same logical state. this is controlled by the bzop bit of the bzcr. subcl ck bzcr bzof bzfs2 bzop r 4 stage divider subcl (32 khz) subcl / 4 (8 khz) subcl / 8 (4 khz) subcl / 16 (2khz) bzfs1 r r r buz nbuz 4 :1 mux 96 11550 figure 40. buzzer module
m44c510 telefunken semiconductors rev. a2, 13-jan-98 44 (57) buz nbuz buz nbuz buzzer off bzop=1 bzop=0 96 11551 figure 41. buzzer waveform buzzer control register (bzcr) subport address (indirect write access): 'a'hex bit 3 bit 2 bit 1 bit 0 bzcr bzfs2 bzfs1 bzop bzof reset value: 1111b bzfs2, bzfs2 buzzer frequency select code bzop buzzer output stop state bzof buzzer off/on table 21.buzzer control register (bzcr) code 3 2 1 0 function x x x 0 buzzer on x x x 1 buzzer off x x 0 x buzzer output stop state: bp42 = bp43 = low x x 1 x buzzer output stop state: bp42 = bp43 = high 0 0 x x buzzer frequency: 32 khz (= subcl) 0 1 x x buzzer frequency: 8 khz (= subcl / 4) 1 0 x x buzzer frequency: 4 khz (= subcl / 8) 1 1 x x buzzer frequency: 2 khz (= subcl / 16)
m44c510 telefunken semiconductors rev. a2, 13jan98 45 (57) 2.7 emulation all marc4 controllers have a special emulation mode. it is activated by setting the te pin to logic high level after reset. in this mode, the internal cpu core is inactive and the i/o bus is available via port 0 and port 1 to allow the emulator the access to the on-chip peripherals. the emulator contains a special emulation cpu with a marc4 core and additional breakpoint logic and takes over the core function. the basic function of the emulator is to evaluate the customer's program and hardware in real time. core target chip evc eprom core tcl clock tcl reset nrst mode te nrst tcl data address i/ocontrolbus i/obus application port 1 port 0 96 11552 port 1 port 0 nrst figure 42. emulation
m44c510 telefunken semiconductors rev. a2, 13-jan-98 46 (57) 3 electrical characteristics 3.1 absolute maximum ratings voltages are given relative to v ss . parameters symbol value unit supply voltage v dd 0.3 to + 6.5 v input voltage (on any pin) v in v ss 0.3 v in v dd +0.3 v output short circuit duration t short indefinite s operating temperature range t amb 40 to +85 c storage temperature range t stg 65 to +150 c thermal resistance (dip40) r thja 110 k/w soldering temperature (t 10 s) t sld 260 c stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at any condition above those indicated in the op- erational section of these specification is not implied. exposure to absolute maximum rating condition for an extended period may affect device reliability. all inputs and outputs are protected against high electrostatic volt- ages or electric fields. however, precautions to minimize the build-up of electrostatic charges during handling are recommended. reliability of operation is enhanced if un- used inputs are connected to an appropriate logic voltage level (e.g. v dd ). 3.2 dc operating characteristics supply voltage v dd = 5 v, v ss = 0 v, t amb = 25 c unless otherwise specified. parameters test conditions / pins symbol min. typ. max. unit power supply active current (cpu active, rc osc. with ext. r 200 k f syscl = 2 mhz v dd = 2.4 v, note 1 v dd = 5.0 v v dd = 6.2 v, note 1 i dd 0.35 1.0 1.25 ma ma ma power down current (cpu sleep, rc oscillator active, subcl = syscl/64) f syscl = 2 mhz v dd = 2.4 v, note 1 v dd = 5.0 v v dd = 6.2 v, note 1 i pd 10 20 25 m a m a m a sleep current (cpu sleep, syscl stopped, 32 khz osc. activ) v dd = 2.4 v, note 1 v dd = 5.0 v v dd = 6.2 v, note 1 i sleep 0.4 1.0 1.2 0.7 1.5 1.8 m a m a m a parameters test conditions / pins symbol min. typ. max. unit power-on reset threshold voltage por threshold voltage v por 1.8 2.0 v por hysteresis note 1 v por 0.25 0.3 v schmitt-trigger input voltage: negative-going threshold voltage v dd = 2.4 to 6.2 v v t v ss 0.3*v dd v positive-going threshold voltage v dd = 2.4 to 6.2 v v t+ 0.7*v dd v dd v hysteresis (vt+ vt) v dd = 2.4 to 6.2 v v h 0.1*v dd note 1: parameter not subject to production test
m44c510 telefunken semiconductors rev. a2, 13jan98 47 (57) input pins: nrst and te parameters test conditions / pins symbol min. typ. max. unit input voltage low v dd = 2.4 to 6.2 v v il v ss 0.2*v dd v input voltage high v dd = 2.4 to 6.2 v v ih 0.8* v dd v dd v input nrst with pull-up resistor input low current v dd = 2.4 v, v il = v ss v dd = 5.0 v i il 100 250 125 320 150 400 m a m a input te with pull-down resistor input high current v dd = 2.4 v, v ih = v dd v dd = 5.0 v i ih 15 200 30 260 50 300 m a m a all bidirectional ports and tim1 parameters test conditions / pins symbol min. typ. max. unit input voltage low v dd = 2.4 to 6.2 v v il v ss 0.2*v dd v input voltage high v dd = 2.4 to 6.2 v v ih 0.8* v dd v dd v input low current (pull-up) v dd = 2.4 v, v il = v ss v dd = 5.0 v i il 1.0 6.0 1.5 8.5 2.5 12.0 m a m a input high current (pull-down) v dd = 2.4 v, v ih = v dd v dd = 5.0 v i ih 1.0 4.0 1.3 3.0 10.0 m a m a output low current dr = 1 v dd = 2.4 v v ol = 0.2*v dd v dd = 5.0 v i ol 0.7 2.8 0.9 3.5 1.1 4.2 ma ma output low current dr = 4 v dd = 2.4 v v ol = 0.2*v dd v dd = 5.0 v i ol 2.8 10.5 3.5 13.1 4.2 15.7 ma ma output low current dr = 12 v dd = 2.4 v v ol = 0.2*v dd v dd = 5.0 v i ol 6.8 28 8.5 34.4 10.2 40.8 ma ma output high current dr = 1 v dd = 2.4 v v oh = 0.8*v dd v dd = 5.0 v i oh 0.5 1.8 0.6 2.2 0.7 2.6 ma ma output high current dr = 4 v dd = 2.4 v v oh = 0.8*v dd v dd = 5.0 v i oh 1.7 6.1 2.1 7.6 2.5 9.1 ma ma output high current dr = 12 v dd = 2.4 v v oh = 0.8*v dd v dd = 5.0 v i oh 4.4 16.5 5.5 20.5 6.6 24.7 ma ma bidirectional port bpa0...bpa3, bpb0...bpb3 parameters test conditions / pins symbol min. typ. max. unit input low current (30 k pull-up) v dd = 2.4 v, v il = v ss v dd = 5.0 v i il 20 120 27 160 40 200 m a m a bidirectional port bp60 and bp61 (intx, inty) parameters test conditions / pins symbol min. typ. max. unit input low current (2 k pull-up) v dd = 2.4 v, v il = v ss v dd = 5.0 v i il 0.2 1.4 0.35 1.7 0.65 2.5 ma ma
m44c510 telefunken semiconductors rev. a2, 13-jan-98 48 (57) 3.3 ac characteristics supply voltage v dd = 2.4 to 6.2 v, v ss = 0 v, t amb = 25 c unless otherwise specified. parameters test conditions / pins symbol min. typ. max. unit timer input timing tim1, bp40 and bp41 timer input clock f timx 4 10 mhz timer input low time rise / fall time < 10 ns t til 50 ns timer input high time rise / fall time < 10 ns t tih 50 ns interrupt request input timing int. request low time rise / fall time < 10 ns t irl 50 ns int. request high time rise / fall time < 10 ns t irh 50 ns system clock sclin input clock rise / fall time < 10 ns f 4 10 mhz start-up time f x = 4 mhz, v dd = 3.0 v t sx 10 20 ms reset timing power-on reset time v dd v por t por 200 500 m s nrst input low time t nrst 4*syscl m s rc oscillator external resistor frequency note 1; r ext = 200 k f rce 1.8 2.0 2.2 mhz stability note 1; v dd = 3 to 5.5 v d f/f 5 % 32-khz oscillator start-up time av dd = 3.0 v t sq 0.5 1 s stability note 2; av dd = 100 mv d f/f 0.1 ppm integrated input / output capacitances c in c out 20 20 pf pf crystal characteristics l c1 rs c0 oscin oscout equivalent circuit 96 11553 sclin sclout figure 43. crystal equivalent circuit parameters test conditions / pins symbol min. typ. max. unit 32-khz crystal crystal frequency f x 32.768 khz series resistance rs 30 50 k static capacitance c0 1.5 pf dynamic capacitance c1 3 ff load capacitance c l 10 12.5 pf 4 mhz crystal crystal frequency f x 4 4.192 mhz series resistance rs 30 50 static capacitance c0 2 4.5 pf dynamic capacitance c1 3 15 ff
m44c510 telefunken semiconductors rev. a2, 13jan98 49 (57) r ext m44c510 sclin v dd 96 12372 figure 44. clock generation with external resistor 0 500 1000 1500 2000 2500 3000 3500 2 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 syscl ( khz ) v dd ( v ) 96 12373 figure 45. internal rcoscillator frequency = f (v dd ) 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 40 20 0 20 40 60 80 syscl ( mhz ) t amb ( c ) v dd = 5 v v dd = 3 v 96 12374 figure 46. internal rcoscillator frequency = f (t amb ) 100 1000 10000 100 1000 10000 syscl ( khz) r ext (k ) v dd = 5 v 96 12375 figure 47. syscl = f (r ext) 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 syscl ( khz) vdd ( v ) rext = 220 k rext = 470 k rext = 2.2 m 96 12376 figure 48. syscl = f (v dd , r ext ) 1900 1950 2000 2050 2100 10 10 30 50 70 90 110 syscl ( khz ) t amb ( c ) v dd = 5 v v dd = 3 v 96 12477 figure 49. syscl = f (t amb ); r ext = 220k
m44c510 telefunken semiconductors rev. a2, 13-jan-98 50 (57) 0 5 10 15 20 25 30 0 0.5 1.0 1.5 2.0 2.5 3.0 i ( ma) v ol ( v ) ol v dd = 3 v dr = 12 dr = 4 dr = 1 96 12378 figure 50. typical low output driver 0 10 20 30 40 50 60 70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i ( ma) v ol ( v ) ol v dd = 5 v dr = 12 dr = 4 dr = 1 96 12379 figure 51. typical low output driver 0 0.5 1.0 1.5 2.0 2.5 40 20 0 20 40 60 80 v ( v ) t amb ( c ) v pdown v por 96 11559 por figure 52. power-on hysteresis = f (t amb ) 0 5 10 15 20 0 0.5 1.0 1.5 2.0 2.5 3.0 i ( ma ) v dd v oh ( v ) oh v dd = 3 v dr = 1 dr = 12 dr = 4 96 12380 figure 53. typical high output driver 0 10 20 30 40 50 0 1.0 2.0 3.0 4.0 5.0 i ( ma ) v dd v oh ( v ) oh v dd = 5 v dr = 1 dr = 12 dr = 4 96 12381 figure 54. typical high output driver
m44c510 telefunken semiconductors rev. a2, 13jan98 51 (57) 4 pad layout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 bp40 bp00 bp01 bp02 bp03 bpa0 sclin vss oscin oscout vdd bp73 25 26 27 28 bp70 bp71 bp72 te nrst bpb0 bpb1 bpb2 bpb3 bp41 m44c510 bp43 bp42 29 30 31 34 35 36 37 38 39 40 41 bpa1 bpa2 bpa3 bp10 bp11 bp12 bp13 tim1 bp53 bp50 bp51 bp52 avdd vss sclout bp61 bp60 96 11554 22 bpc0 bpc1 32 33 42 43 die size: 2.44 x 2.32 mm pad size: 100 x 100 m thickness: 480 25 m ( 19 1 mil) figure 55. pad assignments table 22.pad coordinates pad no. name x-coord y-coord pad no. name x-coord y-coord 1 vss 0.0 0.0 22 bpc0 1863.1 1931.6 2 sclin 0.0 202.6 23 te 2093.0 1931.6 3 sclout 0.0 352.6 24 bpc1 2103.2 1675.8 4 bp61 0.0 502.6 25 tim1 2103.2 1525.8 5 bp60 0.0 652.6 26 bp00 2103.2 1375.8 6 bpb3 0.0 802.6 27 bp01 2103.2 1225.8 7 bpb2 0.0 952.6 28 bp02 2103.2 1075.8 8 bpb1 0.0 1102.6 29 bp03 2103.2 925.8 9 bpb0 0.0 1252.6 30 bp40 2103.2 757.5 10 avdd 0.0 1402.6 31 bp41 2103.2 607.5 11 oscin 9.8 1931.6 32 bp42 2103.2 457.5 12 oscout 263.0 1931.6 33 bp43 2103.2 307.0 13 nrst 513.1 1931.6 34 vdd 2103.2 0.0 14 bpa0 663.1 1931.6 35 bp50 1705.2 0.0 15 bpa1 813.1 1931.6 36 bp51 1555.2 0.0 16 bpa2 963.1 1931.6 37 bp52 1405.2 0.0 17 bpa3 1113.1 1931.6 38 bp53 1255.2 0.0 18 bp10 1263.1 1931.6 39 vss 923.5 0.0 19 bp11 1413.1 1931.6 40 bp70 755.5 0.0 20 bp12 1563.1 1931.6 41 bp71 605.5 0.0 21 bp13 1713.1 1931.6 42 bp72 455.5 0.0 43 bp73 305.5 0.0
m44c510 telefunken semiconductors rev. a2, 13-jan-98 52 (57) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 23 22 21 24 sclin bp13 bp00 bp12 bp11 bp10 oscin oscout bp01 bp02 bp03 nrst vss vdd bp43 bp42 bp41 bp40 bpb3 bpb2 bpb1 bpb0 bp70 bp71 bp72 bp73 bp53 bp52 bp51 bp50 tim1 bpa3 bpa2 bpa1 bpa0 te avdd bp61 [inty] bp60 [intx] sclout m44c510p40 96 11516 figure 56. pin connections for dip 40 13043 technical drawings according to din specifications 4.06 3.56 package dip40 (cei) dimensions in mm 15.49 14.99 3.81 3.18 0.89 0.38 13.97 13.46 17.02 15.24 0.38 0.20 2.54 0.58 0.38 1.65 1.14 48.26 52.58 51.82 40 21 1 20
m44c510 telefunken semiconductors rev. a2, 13jan98 53 (57) 13040 technical drawings according to din specifications package sso44 dimensions in mm 0.25 0.10 0.3 0.8 18.05 17.80 16.8 2.35 9.15 8.65 7.50 7.30 10.50 10.20 0.25 44 23 1 22
m44c510 telefunken semiconductors rev. a2, 13-jan-98 54 (57) 5 application examples port a port b port 1 port 4 port 5 port 7 sclin bp02 bp01 bp00 8 16 pc keyboard matrix m44c510 v v v dd dd ss bp60 bp61 + 5 v data clock gnd shield pc connector + 5 v 220 k lock shift num 3 * led 96 11555 figure 57. m44c510 as keyboard controller port a port b port 5 sclin bp73 (power save) bp72 bp70 m44c510 v v dd ss 470 k bp71 com0 com1 com2 100 nf 2.2 v ... 3.6 v gnd 3 x 470 k 3 x 470 k v dd 96 12382 figure 58. driving a lcd panel with 1/3 duty
m44c510 telefunken semiconductors rev. a2, 13jan98 55 (57) 6 ordering information please select the option setting from the list below and insert the rom file name and the rom crc. dr means driver ratio (= ma @ 3 v) and can be choosen from 1 to 12, however, the whole port must have the same value. port 0 dr =_____ cmos bp00 pull-up pull-down bp01 pull-up pull-down bp02 pull-up pull-down bp03 pull-up pull-down port 1 dr =_____ bp10 cmos pull-up open drain [n] pull-down open drain [p] bp11 cmos pull-up open drain [n] pull-down open drain [p] bp12 cmos pull-up open drain [n] pull-down open drain [p] bp13 cmos pull-up open drain [n] pull-down open drain [p] port 4 dr =_____ bp40 cmos pull-up open drain [n] pull-down open drain [p] bp41 cmos pull-up open drain [n] pull-down open drain [p] bp42 cmos pull-up open drain [n] pull-down open drain [p] bp43 cmos pull-up open drain [n] pull-down open drain [p] port 5 dr =_____ bp50 cmos pull-up open drain [n] pull-down open drain [p] bp51 cmos pull-up open drain [n] pull-down open drain [p] bp52 cmos pull-up open drain [n] pull-down open drain [p] bp53 cmos pull-up open drain [n] pull-down open drain [p] port 6 dr =_____ bp60 cmos pull-up open drain [n] pull-down open drain [p] pull-up (2 k) bp61 cmos pull-up open drain [n] pull-down open drain [p] pull-up (2 k) port 7 dr =_____ bp70 cmos pull-up open drain [n] pull-down open drain [p] bp71 cmos pull-up open drain [n] pull-down open drain [p] bp72 cmos pull-up open drain [n] pull-down open drain [p] bp73 cmos pull-up open drain [n] pull-down open drain [p] port c dr =_____ bpc0 cmos pull-up open drain [n] pull-down open drain [p] bpc1 cmos pull-up open drain [n] pull-down open drain [p]
m44c510 telefunken semiconductors rev. a2, 13-jan-98 56 (57) port a dr =_____ bpa0 cmos pull-up open drain [n] pull-down open drain [p] pull-up (30 k) bpa1 cmos pull-up open drain [n] pull-down open drain [p] pull-up (30 k) bpa2 cmos pull-up open drain [n] pull-down open drain [p] pull-up (30 k) bpa3 cmos pull-up open drain [n] pull-down open drain [p] pull-up (30 k) port b dr =_____ bpb0 cmos pull-up open drain [n] pull-down open drain [p] pull-up (30 k) bpb1 cmos pull-up open drain [n] pull-down open drain [p] pull-up (30 k) bpb2 cmos pull-up open drain [n] pull-down open drain [p] pull-up (30 k) bpb3 cmos pull-up open drain [n] pull-down open drain [p] pull-up (30 k) tim1 dr =_____ cmos open drain [n] pull-up open drain [p] pull-down bpareset no bpa0 & bpa1 bpa0 & bpa1 & bpa2 bpa0 & bpa1 & bpa2 & bpa3 watchdog 1 / 2 s disabled 1 s 2 s syscl type r extern rc intern 4 mhz crystal oscillator 4 mhz ceramic resonator sleep clk syscl running syscl stopped subclk syscl / 64 32 khz crystal oscin no integrated capacitance internal cap ( _ pf) oscout no intergrated capacitance internal cap ( _ pf) sclin no integrated capacitance internal cap ( _ pf) sclout no integrated capacitance internal cap ( _ pf) package dit dow sso44 dip40 file:____________. hex crc: _____________ hex approval date: ____________ signature: _______________
m44c510 telefunken semiconductors rev. a2, 13jan98 57 (57) we reserve the right to make changes to improve technical design without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use temic products for any unintended or unauthorized application, the buyer shall indemnify temic against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. temic telefunken microelectronic gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 ( 0 ) 7131 67 2831, fax number: 49 ( 0 ) 7131 67 2423

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